Semiconductor packages come in many varieties based on the intended application. A split die semiconductor package is a casing containing two semiconductor dies that provides protection against impact and holds the contact pins or leads that are used to connect from external circuits to the package. The split die architecture requires Die-to-Die (D2D) interconnects with very fine line and spaces (L/S—typically 1/1, 2/2). These fine line and spacing parameters are expensive to achieve and create problems with the requirement for exact placement of the die to align with the fine L/S routing. Conventional split die semiconductor packages either require a silicon interposer that acts like a bridge or embedded wafer level package (eWLP) with multiple redistribution layers (RDLs) that have fine line and space parameters. However, conventional interposers increase the height of the package, which is undesirable, and embedded multiple RDLs are complicated and expensive to manufacture plus they are not suitable for high volume manufacturing.
Accordingly, there are long-felt industry needs for methods that improve upon conventional methods including the improved methods and apparatus provided hereby.
The inventive features that are characteristic of the teachings, together with further features and advantages, are better understood from the detailed description and the accompanying figures. Each of the figures is provided for the purpose of illustration and description only, and does not limit the present teachings.